{"id":11732,"date":"2026-10-16T02:48:27","date_gmt":"2026-10-15T23:48:27","guid":{"rendered":"https:\/\/etti.upb.ro\/?p=11732"},"modified":"2026-10-16T02:48:27","modified_gmt":"2026-10-15T23:48:27","slug":"implementarea-circuitelor-digitale-2026","status":"publish","type":"post","link":"https:\/\/etti.upb.ro\/en\/2026\/10\/16\/implementarea-circuitelor-digitale-2026\/","title":{"rendered":"Implementation of Digital Circuits"},"content":{"rendered":"<style>.etti-catalog-article{max-width:100%;line-height:1.65;overflow-wrap:anywhere}.etti-catalog-article .etti-archive-note{font-size:.9rem;color:#4b5563;border-left:3px solid #235c83;padding:.5rem .8rem;margin:0 0 1.2rem}.etti-catalog-article .etti-archive-note p{margin:.2rem 0}.etti-catalog-article dl{margin:1rem 0}.etti-catalog-article dt{font-weight:700;margin:1rem 0 .15rem}.etti-catalog-article dd{margin:0 0 .65rem}.etti-catalog-article ul{padding-left:1.4rem}.etti-catalog-article figure{margin:1.4rem 0;max-width:100%}.etti-catalog-article figure img{display:block;max-width:100%;height:auto;margin:0 auto}.etti-catalog-article figcaption{font-size:.9rem;color:#4b5563;margin-top:.5rem;text-align:center}.etti-catalog-article h2{font-size:1.6rem!important;line-height:1.3;margin-top:1.6rem}.etti-catalog-article .etti-event-state{border-left:3px solid #b46b15;background:#fff8ed;padding:.7rem .9rem}<\/style>\n<article class=\"etti-catalog-article\"><aside class=\"etti-archive-note\"><p>Activity Archive \u00b7 2026<\/p><p><a href=\"\/en\/activitati-si-oportunitati\/\">Activities and Opportunities<\/a> \/ <a href=\"\/en\/activitati-si-oportunitati\/cursuri-scoli-concursuri\/\">Courses, Schools, and Contests<\/a><\/p><p>The information and terms of participation apply to the edition described.<\/p><\/aside><p>An applied course on the transition from RTL code to a verified chip layout ready for manufacturing. The focus is on the physical implementation, from the netlist generated by RTL code synthesis to the final layout and its verification, with an emphasis on operating frequency, power consumption, and area.<\/p>\n<p>Participants will use Cadence Innovus for the physical implementation of digital integrated circuits and Tcl scripts to automate design stages. In the lab, they will gradually build their own project, working through the entire implementation workflow for a digital block.<\/p>\n<p>Topics: ASIC design flow and the Tcl language; floorplanning and power distribution; cell placement and circuit optimization; clock signal distribution; routing and delay analysis; physical verification and final checks.<\/p>\n<h2>Details<\/h2>\n<dl><dt>Organizer<\/dt><dd>Course developed in collaboration with Marvell.<\/dd><dt>Activity Schedule<\/dt><dd>7 lectures, each lasting 2 hours, and 7 lab sessions, each lasting 2 hours, for a total of 28 hours.<\/dd><dt>Participation<\/dt><dd>Third- and fourth-year students. Prerequisite: CID.<\/dd><\/dl>\n<h2>Additional details<\/h2>\n<p>Lab instructors: \u0218tefan Catrinoiu (Marvell) and Alex C\u0103linescu (AMPLIPH).<\/p><\/article>","protected":false},"excerpt":{"rendered":"<p>An applied course on the transition from RTL code to a verified chip layout ready for manufacturing. The focus is on the physical implementation, from the netlist generated by RTL code synthesis to the final layout and its verification, with an emphasis on operating frequency, power consumption, and area.<\/p>","protected":false},"author":5,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","_eb_attr":"","_uag_custom_page_level_css":"","footnotes":""},"categories":[236,237,239],"tags":[246],"class_list":["post-11732","post","type-post","status-publish","format-standard","hentry","category-activitati-si-oportunitati","category-activitati-cursuri-scoli-concursuri","category-activitati-laboratoare-parteneri","tag-activitati-2026"],"featured_image_src":null,"author_info":{"display_name":"Cr\u0103ciunescu R\u0103zvan-Eusebiu","author_link":"https:\/\/etti.upb.ro\/en\/author\/razvan-craciunescu\/"},"acf":[],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"elegant_blocks_team_1":false,"elegant_blocks_blog_1":false,"elegant_blocks_slider_1":false,"1536x1536":false,"2048x2048":false,"trp-custom-language-flag":false,"bizberg_medium":false,"bizberg_gallery":false,"bizberg_blog_list":false,"bizberg_detail_image":false,"bizberg_portfolio_homepage":false,"bizberg_blog_list_no_sidebar_1":false,"bizberg_detail_image_no_sidebar":false},"uagb_author_info":{"display_name":"Cr\u0103ciunescu R\u0103zvan-Eusebiu","author_link":"https:\/\/etti.upb.ro\/en\/author\/razvan-craciunescu\/"},"uagb_comment_info":0,"uagb_excerpt":"Curs aplicat despre trecerea de la codul RTL la un layout de cip verificat \u0219i preg\u0103tit pentru trimiterea la fabrica\u021bie. Accentul cade pe implementarea fizic\u0103, de la netlistul ob\u021binut prin sinteza codului RTL p\u00e2n\u0103 la layout-ul final \u0219i verificarea acestuia, urm\u0103rind frecven\u021ba de func\u021bionare, consumul \u0219i aria ocupat\u0103.","_links":{"self":[{"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/posts\/11732","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/comments?post=11732"}],"version-history":[{"count":2,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/posts\/11732\/revisions"}],"predecessor-version":[{"id":12151,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/posts\/11732\/revisions\/12151"}],"wp:attachment":[{"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/media?parent=11732"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/categories?post=11732"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/etti.upb.ro\/en\/wp-json\/wp\/v2\/tags?post=11732"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}