An applied course on the transition from RTL code to a verified chip layout ready for manufacturing. The focus is on the physical implementation, from the netlist generated by RTL code synthesis to the final layout and its verification, with an emphasis on operating frequency, power consumption, and area.

Participants will use Cadence Innovus for the physical implementation of digital integrated circuits and Tcl scripts to automate design stages. In the lab, they will gradually build their own project, working through the entire implementation workflow for a digital block.

Topics: ASIC design flow and the Tcl language; floorplanning and power distribution; cell placement and circuit optimization; clock signal distribution; routing and delay analysis; physical verification and final checks.

Details

Organizer

Course developed in collaboration with Marvell.

Activity Schedule

7 lectures, each lasting 2 hours, and 7 lab sessions, each lasting 2 hours, for a total of 28 hours.

Participation

Third- and fourth-year students. Prerequisite: CID.

Additional details

Lab instructors: Ștefan Catrinoiu (Marvell) and Alex Călinescu (AMPLIPH).