Applied chip design course using the open-source SKY130 PDK and Cadence Virtuoso. Modules: logic gates and testing; automated physical implementation (Layout View); optimization for low power consumption and high speed; sequential circuits and special-function blocks, including noise filtering.
Details
- Organizer
- Marius Enăchescu, ETTI Faculty, POLITEHNICA Bucharest.
- Activity Schedule
- September 28 and 30, 2026, 9:00 a.m.–1:00 p.m.; different modules on each day.
- Location and Format
- VLSI Lab, Room B120, ETTI; work is done on the lab's computers.
- Participation
- Primarily first- and second-year students, but master’s students and faculty members are also welcome. Participation in only some modules is permitted, as confirmed by the organizer.
- Benefits
- Diploma/certificate of participation with a UPB registration number and a copy of the book *Accelerating Semiconductor Research: Leveraging Open-Source PDK to Prepare Industry-Ready Engineers*.
- Costs
- Free.
Additional details
Training will take place in September 2026 for the 2027 edition of TIE nano. The modules for the two days are different; the activities make use of the lab's computers.