Digital System Design Project I

Titular Curs: Conf. dr. ing. Zoltan HASCSI
Titular laborator: Conf. dr. ing. Zoltan HASCSI

Design, verification, implementation, and test of a complex digital system, with a parallel processor, memory system and access interface. Part I concerns the design and verification of a pipeline RISC processor, with parallel execution units and advanced management of data and control dependencies. The project also aims to introduce students to state-of-the-art design flow, hardware-software co-design, golden model verification, using one of the industry standard EDA tool and employing the Verilog HDL language.