Digital System Design Project II

Titular Curs: Conf. dr. ing. Zoltan HASCSI
Titular laborator: Conf. dr. ing. Zoltan HASCSI

Design, verification, implementation, and test of a complex digital system, with a parallel processor, memory system and access interface. Part II concerns the design of a programmable memory controller, the integration of the processor, its memories, the memory controller and an I/O interface into a complete system, using various protocols (native, AXI, UART), the implementation of the whole system into an FPGA development board, and testing the system communication with a host computer.